PLFM_RADAR: Building a 10.5 GHz Phased Array Radar System with Open-Source Hardware

Hook

With nearly 20,000 GitHub stars, PLFM_RADAR is one of the most popular radar projects ever released as open-source hardware—despite requiring FPGA firmware development, microwave PCB design skills, and a four-figure component budget.

Context

Phased array radar technology has traditionally been locked behind military contracts and six-figure commercial systems. While software-defined radio platforms like USRP and HackRF democratized RF experimentation below 6 GHz, coherent radar systems operating in X-band (8-12 GHz) remained inaccessible to researchers, universities, and advanced makers. The few open-source radar projects that existed either operated at lower frequencies with limited resolution, lacked true beamforming capabilities, or published only partial designs without manufacturing files.

PLFM_RADAR (officially named AERIS-10) changes this by releasing complete hardware schematics, PCB Gerbers, FPGA firmware, and control software under CERN-OHL-P and MIT licenses. The project targets practical applications like drone detection, atmospheric sensing, and radar research education—use cases where commercial solutions cost $50k-$500k but where a $3k-$8k open-source system could suffice. The 'low-cost' descriptor is relative: you're comparing against Raytheon and Thales, not Arduino projects.

Technical Insight

AERIS-10 implements a complete radar signal chain across three processing tiers. An STM32F746 microcontroller orchestrates system initialization, I²C bus management for 40+ peripherals, and closed-loop bias control for power amplifiers. A Xilinx XC7A50T FPGA handles real-time signal processing at sample rates up to 250 MSPS. A Python GUI built on PyQt5 provides visualization, recording, and parameter adjustment through USB 3.0.

The transmit chain starts with PLFM (polynomial linear frequency modulated) waveform generation via an AD9172 DAC. Unlike standard LFM chirps, PLFM waveforms offer lower sidelobe levels in compressed pulses—critical for detecting weak targets near strong returns. The baseband signal feeds an ADF4382 PLL synthesizer that upconverts to 10.5 GHz using a precision 100 MHz reference from an AD9523-1 clock distribution IC. The signal then splits 16 ways into ADAR1000 beamforming ICs, which apply phase and amplitude weights for electronic beam steering across ±45 degrees without mechanical movement.

The receive chain mirrors this topology in reverse: 16 antenna elements feed ADAR1000 chips configured for receive beamforming, downconvert through ADTR1107 integrated transceivers, and digitize via AD9208 ADCs. The FPGA firmware implements the full radar DSP pipeline:

# Simplified Python interface to FPGA processing chain
class RadarProcessor:
    def configure_processing(self, config):
        # AGC parameters
        self.write_reg(0x1000, config['agc_attack_time'])
        self.write_reg(0x1004, config['agc_decay_time'])
        
        # Pulse compression matched filter coefficients
        # PLFM waveform pre-computed and uploaded
        self.upload_filter_taps(0x2000, config['matched_filter'])
        
        # Doppler FFT configuration
        fft_size = config['cpi_pulses']  # Coherent processing interval
        self.write_reg(0x3000, fft_size)
        self.write_reg(0x3004, config['window_function'])
        
        # MTI filter (3-pulse canceller)
        self.write_reg(0x4000, 0x01)  # Enable MTI
        self.write_reg(0x4004, config['mti_notch_width'])
        
        # CFAR detector thresholds
        self.write_reg(0x5000, config['cfar_guard_cells'])
        self.write_reg(0x5004, config['cfar_training_cells'])
        self.write_reg(0x5008, config['cfar_pfa'])  # Probability of false alarm

The FPGA processes each pulse through hybrid AGC with separate fast and slow loops, decimates from 250 MSPS to 50 MSPS, applies matched filtering for pulse compression (improving SNR by 10log₁₀(bandwidth × pulse_width)), performs Doppler FFT across coherent pulse trains, implements three-pulse MTI cancellation to reject ground clutter, and runs cell-averaging CFAR detection to maintain constant false alarm rates across varying noise conditions.

Beamforming control demonstrates the system's sophistication. Each ADAR1000 manages four antenna elements with independent 6-bit phase shifters (5.6° resolution) and 7-bit gain control. The STM32 firmware calculates phase tapers in real-time:

// Simplified beamforming calculation from STM32 firmware
void calculate_beam_weights(float azimuth_deg, float elevation_deg) {
    float k = 2.0 * M_PI / LAMBDA;  // Wave number at 10.5 GHz
    
    for (int elem = 0; elem < 16; elem++) {
        // Element position in array coordinates
        float x = element_positions[elem].x;
        float y = element_positions[elem].y;
        
        // Phase delay for desired beam direction
        float phase_delay = k * (x * sin(azimuth_deg * DEG2RAD) + 
                                  y * sin(elevation_deg * DEG2RAD));
        
        // Convert to 6-bit phase shifter code
        uint8_t phase_code = (uint8_t)((phase_delay / (2*M_PI)) * 64) & 0x3F;
        
        // Taylor amplitude taper for -30dB sidelobes
        uint8_t gain_code = taylor_window[elem];
        
        // Program ADAR1000 via SPI
        adar1000_set_channel(elem/4, elem%4, phase_code, gain_code);
    }
}

The two hardware variants trade off cost versus capability. The 3km version uses an 8×16 patch antenna array with 2W transmit power, suitable for short-range drone detection or laboratory experiments. The 20km version upgrades to a 32×16 slotted waveguide array with 10W GaN amplifiers (likely CREE CMPA1D1E100F or similar), providing 25dB additional link budget. Both share the same core electronics, allowing iterative development: prototype with patches, then upgrade antennas and amplifiers for extended range.

Thermal management proves critical at these power levels. The design includes eight thermistors monitoring critical components (GaN PAs, ADAR1000 chips, FPGA), with the STM32 controlling PWM fan speed and triggering protection shutdowns above 85°C. Power amplifier bias uses closed-loop Idq control: current-sense amplifiers measure each PA's quiescent current, the STM32 adjusts gate bias via DACs to maintain optimal linearity across temperature, preventing thermal runaway while maximizing efficiency.

Gotcha

The repository's alpha status means incomplete documentation and work-in-progress subsystems. You'll find hardware schematics and PCB layouts, but assembly instructions are sparse—expect to reverse-engineer grounding strategies, determine appropriate PCB stackups for microwave frequencies (likely 6-layer with buried stripline), and source equivalent components when specified parts face long lead times. The FPGA firmware appears partially complete: pulse compression and beamforming modules exist, but integration with the full processing chain requires VHDL/Verilog skills. The Python GUI provides basic visualization, but advanced features like SAR imaging or track-while-scan remain unimplemented.

The 'PLSQL' language tag is clearly erroneous—GitHub's auto-detection likely misclassified configuration files. This metadata error hints at organizational issues: file structures may be inconsistent, commit messages sparse, and architectural decisions undocumented. More critically, the radar requires specialized test equipment for validation: a calibrated RF signal generator for receiver testing, spectrum analyzer for transmit verification, and vector network analyzer for antenna characterization. Without access to this $20k-$100k lab setup, you'll struggle to debug performance issues or verify your build matches specifications. Component costs alone exceed $3k for the patch array version, rising to $6k-$8k with GaN amplifiers—before considering PCB fabrication, mechanical housing, or test equipment time.

Verdict

Use PLFM_RADAR if you're a university research lab with RF/microwave facilities, an experienced hardware engineer exploring radar DSP techniques, or a well-funded maker who already owns FPGA development tools and microwave test equipment. The hardware architecture is technically sound and the open-source release is genuinely comprehensive compared to typical academic radar publications. This project shines for educational environments where students can learn beamforming theory, FPGA signal processing, and radar system integration on real hardware. Skip if you need a working radar system within six months, lack FPGA firmware experience, don't have access to microwave test equipment, or can't budget $5k-$10k for a single prototype build. Also skip if you expect plug-and-play operation—you're signing up to become a radar system engineer, not just assembling someone else's finished design. For practical drone detection today, consider commercial modules like Echodyne MESA or Fortem TrueView despite their cost premium.